MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 447

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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DDRQA — Port QA Data Direction Register
QACR0 — QADC64 Control Register 0
13.12.5 Port Data Direction Register
RESET:
13.12.6 QADC64 Control Register 0 (QACR0)
RESET:
MPC555
USER’S MANUAL
DDQA7
Bit(s)
MUX
MSB
MSB
0:7
0
0
0
0
Control register zero establishes the QCLK with prescaler parameter fields and de-
fines whether external multiplexing is enabled. All of the implemented control register
fields can be read or written, reserved fields read zero and writes have no effect. They
are typically written once when the software initializes the QADC64, and not changed
afterwards.
DDQA
RESERVED
DDQA[7:0]
/
1
6
0
1
0
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Name
DDQA
2
5
0
2
0
Bits in this register control the direction of the port QA pin drivers when pins are configured for I/
O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the cor-
responding pin as an input. This register can be read or written at any time.
DDQA
TRG
3
4
0
3
0
Freescale Semiconductor, Inc.
DDQA
Table 13-10 DDRQA Bit Descriptions
4
3
0
4
0
For More Information On This Product,
RESERVED
DDQA
5
2
0
5
0
Go to: www.freescale.com
DDQA
Rev. 15 October 2000
6
1
0
6
0
DDQA
7
0
0
7
0
8
0
8
1
Description
PSH
9
0
9
0
10
10
0
1
RESERVED
11
11
0
1
PSA
12
12
0
0
13
13
0
1
0x30 4C0A
0x30 4C08
0x30 480A
0x30 4808
MOTOROLA
PSL
14
14
0
1
13-35
LSB
LSB
15
15
0
1

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