MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 468

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.5.4 QSMCM Interrupts
MPC555
USER’S MANUAL
The interrupt structure of the IMB3 supports a total of 32 interrupt levels that are time
multiplexed on the IRQB[0:7] lines as seen in
In this structure, all interrupt sources place their asserted level on a time multiplexed
bus during four different time slots, with eight levels communicated per slot. The
ILBS[0:1] signals indicate which group of eight are being driven on the interrupt re-
quest lines.
The QSMCM module is capable of generating one of the 32 possible interrupt levels
on the IMB3. The levels that the interrupt will drive can be programmed into the inter-
rupt request level (ILDSCI and ILQSPI) bits located in the interrupt configuration reg-
ister (QDSCI_IL and QSPI_IL). This value determines which interrupt signal
(IRQB[0:7]) is driven onto the bus during the programmed time slot.
shows a block diagram of the interrupt hardware.
ILBS[1:0]
IMB3 CLOCK
IMB3 IRQ[7:0]
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
Figure 14-2 QSMCM Interrupt Levels
00
For More Information On This Product,
Table 14-3 Interrupt Levels
01
IRQ
7:0
Go to: www.freescale.com
ILBS[0:1]
Rev. 15 October 2000
00
01
10
11
10
IRQ
15:8
23:16
11
IRQ
Levels
16:23
24:31
Figure
8:15
0:7
31:24
00
IRQ
14-2.
01
IRQ
7:0
10
11
Figure 14-3
MOTOROLA
14-6