MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 252

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

7.5 Reset Configuration
7.5.1 Hard Reset Configuration
MPC555
USER’S MANUAL
NOTES:
Bit(s)
13:15
10
11
12
9
1. In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
When a hard reset event occurs, the MPC555 / MPC556 reconfigures its hardware
system as well as the development port configuration The logical value of the bits that
determine its initial mode of operation, are sampled from the following:
If at the sampling time (at HRESET negation) RSTCONF is asserted, then the config-
uration is sampled from the data bus. If RSTCONF is negated and a valid NVM value
exists (CMFCFIG bit HC=0), then the configuration is sampled from the NVM register
in the CMF module. If RSTCONF is negated and no valid NVM value exists (CMFCFIG
bit HC=1), then the configuration word is sampled from the internal default. HC will be
“1” if the internal flash is erased.
tions.
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
• The external data bus pins DATA[0:31]
• An internal default constant (0x0000 0000)
• An internal NVM register value (CMFCFIG)
/
GHRST
GSRST
GPOR
MPC556
Name
ILBC
—
Table 7-3 Reset Status Register Bit Descriptions (Continued)
If the CMFCFIG reset config word is being used, then the flash is au-
tomatically enabled.
Illegal bit change. This bit is set when the MPC555 / MPC556 changes any of the following bits
when they are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than TBD ns
0 = No glitch was detected on the PORESET pin
1 = A glitch was detected on the PORESET pin
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
TBD ns
0 = No glitch was detected on the HRESET pin
1 = A glitch was detected on the HRESET pin
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than TBD ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and
the GSRST bit will be set. The GSRST bit remains set until software clears it. The GSRST bit
can be negated by writing a one to GSRST. A write of zero has no effect on this bit.
0 = No glitch was detected on SRESET pin
1 = A glitch was detected on SRESET pin
Reserved
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Table 7-4
RESET
NOTE
Description
.
summarizes the reset configuration op-
MOTOROLA
7-6