MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 474

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

DDRQS — PORTQS Data Direction Register
14.6.3 PORTQS Data Direction Register (DDRQS)
MPC555
USER’S MANUAL
SET:
MSB
RE-
0
Bit(s)
8:15
DDRQS assigns QSPI pin as an input or an output regardless of whether the QSPI
submodule is enabled or disabled. All QSPI pins are configured during reset as gen-
eral-purpose inputs.
This register does not affect SCI operation. The TXD1 and TXD2 remain output pins
dedicated to the SCI submodules, and the RXD1, RXD2 and ECK pins remain input
pins dedicated to the SCI submodules.
*See bit descriptions in
0
1
2
3
4
5
6
7
1
/
MPC556
QPAPCS3
QPAPCS2
QPAPCS1
QPAPCS0
QPAMOSI
QPAMISO
DDRQS
2
Name
—
—
PQSPAR*
3
Table
Reserved
0 = Pin is assigned QGPIO3
1 = Pin is assigned PCS3 function
0 = Pin is assigned QGPIO2
1 = Pin is assigned PCS2 function
0 = Pin is assigned QGPIO1
1 = Pin is assigned PCS1 function
0 = Pin is assigned QGPIO0
1 = Pin is assigned PCS[0] function
Reserved
0 = Pin is assigned QGPIO5
1 = Pin is assigned MOSI function
0 = Pin is assigned QGPIO4
1 = Pin is assigned MISO function
PORSTQS data direction register. See
(DDRQS).
Freescale Semiconductor, Inc.
4
Table 14-10 PQSPAR Bit Descriptions
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
14-10.
5
Go to: www.freescale.com
Rev. 15 October 2000
6
7
8
0
0
QDD-
PCS3
Description
9
0
14.6.3 PORTQS Data Direction Register
PCS2
QDD-
10
0
PCS1
QDD-
11
0
QDD-
PCS0
12
0
QDD-
SCK
13
0
0x30 5016
MOTOROLA
QDD-
MOSI
14
0
14-12
QDD-
MISO
LSB
15
0