MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 463

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.1 Overview
14.2 Block Diagram
MPC555 / MPC556
USER’S MANUAL
The queued serial multi-channel module (QSMCM) provides three serial communica-
tion interfaces: the queued serial peripheral interface (QSPI) and two serial communi-
cations interfaces (SCI1 and SCI2). These submodules communicate with the CPU
via a common slave bus interface unit (SBIU).
The QSPI is a full-duplex, synchronous serial interface for communicating with periph-
erals and other MCUs. It is enhanced from the original SPI in the QSMCM (queued
serial module) to include a total of 160 bytes of queue RAM to accommodate more re-
ceive, transmit, and control information. The QSPI is fully compatible with the SPI sys-
tems found on other Motorola devices.
The dual, independent SCIs are used to communicate with external devices and other
MCUs via an asynchronous serial bus. Each SCI is a full-duplex universal asynchro-
nous receiver transmitter (UART) serial interface. The original QSMCM SCI is en-
hanced by the addition of an SCI and a common external baud clock source.
The SCI1 has the ability to use the resultant baud clock from SCI2 as the input clock
source for the SCI1 baud rate generator. Also, the SCI1 has an additional mode of op-
eration that allows queuing of transmit and receive data frames. If the queue feature
is enabled, a set of 16 entry queues is allocated for the receive and/or transmit oper-
ation.
Figure 14-1
QUEUED SERIAL MULTI-CHANNEL MODULE
depicts the major components of the QSMCM.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
SECTION 14
MOTOROLA
14-1