MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 87

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

2.4.2 Pad Module Configuration Register (PDMCR)
MPC555
USER’S MANUAL
PDMCR
SLRC0
HARD RESET:
HARD RESET:
Bit(s)
4:5
16
0
0
0
0
1
2
3
6
0 = 3-V bus pins full drive (50-pF load)*
1 = 3-V bus pins reduced drive (25-pF load)
* The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register
The slew rate and weak pull-up/pull-down characteristics of some pins are controlled
by bits in the PDMCR. This register resides in the SIU memory map. The contents of
the PDMCR are illustrated below. The PORESET signal resets all the PDMCR bits
asynchronously.
NOTE:
1. FTPU_PU is only available on mask set K62N and later.
(for the TPU, QADC, USIU (SGPIO), QSPI, TouCAN, QSCI, and MIOS pins).
SLRC
17
/
1
1
0
0
SLRC0
SLRC1
SLRC2
SLRC3
– Pad Module Configuration Register
MPC556
PRDS
Name
—
SLRC
18
2
2
0
0
SLRC0 controls the slew rate of the following modules: TPU, QADC, USIU (SGPIO).
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
SLRC1 controls the slew rate of the QSPI and TouCAN modules.
0 = Slow slew rate for pins. Controls slew rate pins of 50 ns.
1 = Normal slew rate for pins
SLRC2 controls the slew rate of the QSCI module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
SLRC3 controls the slew rate of the MIOS module.
0 = Slow slew rate for pins. Controls slew rate pins of 200 ns.
1 = Normal slew rate for pins
Reserved
The PRDS bit is used to enable or disable the weak pull-up/pull-down devices in the pads related
to SGPIO and all pads related to IMB modules.
PRDS.
0 = Enable pull-up/pull-down devices
1 = Disable pull-up/pull-down devices
SLRC
19
3
3
0
0
Freescale Semiconductor, Inc.
20
4
Reserved
0
0
For More Information On This Product,
Table 2-3 PDMCR Bit Descriptions
21
5
0
0
Go to: www.freescale.com
SIGNAL DESCRIPTIONS
PRDS
Rev. 15 October 2000
22
6
0
0
SPRD
RESERVED
23
7
S
0
0
.
.
FTPU
_PU
24
0
8
0
Description
1
25
0
9
0
Table 2-4
10
26
0
0
illustrates which pins are affected by
11
27
0
0
Reserved
28
12
0
0
29
13
0
0
0x2F C03C
MOTOROLA
30
14
0
0
31
15
2-29
0
0