MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 627

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
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MPC556
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Freescale Semiconductor, Inc.
For More Information On This Product,
Table 17-5 TPU3 Register Map
TPU3 Module Configuration Register (TPUMCR)
See
TPU3 Test Configuration Register (TCR)
Development Support Control Register (DSCR)
See
Development Support Status Register (DSSR)
See
TPU3 Interrupt Configuration Register (TICR)
See
Channel Interrupt Enable Register (CIER)
See
Channel Function Selection Register 0 (CFSR0)
See
Channel Function Selection Register 1 (CFSR1)
See
Channel Function Selection Register 2 (CFSR2)
See
Channel Function Selection Register 3 (CFSR3)
See
Host Sequence Register 0 (HSQR0)
See
Host Sequence Register 1 (HSQR1)
See
Host Service Request Register 0 (HSRR0)
See
Host Service Request Register 1 (HSRR1)
See
Channel Priority Register 0 (CPR0)
See
Channel Priority Register 1 (CPR1)
See
Channel Interrupt Status Register (CISR)
See
Link Register (LR)
Service Grant Latch Register (SGLR)
Decoded Channel Number Register (DCNR)
TPU Module Configuration Register 2 (TPUMCR2)
See
TPU Module Configuration 3 (TPUMCR3)
See
Internal Scan Data Register (ISDR)
TIME PROCESSOR UNIT 3
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Table 17-6
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Table 17-13
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Table 17-14
Table 17-14
Table 17-16
Table 17-17
Table 17-20
Rev. 15 October 2000
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Register
MSB
0
LSB
15
MOTOROLA
17-9