MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 749

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.7.10 Breakpoint Counter B Value and Control Register
COUNTB[16:31] are cleared following reset; COUNTB[0:15] are unaffected by reset.
21.7.11 Exception Cause Register (ECR)
MPC555
USER’S MANUAL
COUNTB — Breakpoint Counter B Value and Control Register
Bit(s)
16:29
30:31
0:15
16
0
0
RESET:
The ECR indicates the cause of entry into debug mode. All bits are set by the hardware
and cleared when the register is read when debug mode is disabled, or if the processor
is in debug mode. Attempts to write to this register are ignored. When the hardware
sets a bit in this register, debug mode is entered only if debug mode is enabled and
the corresponding mask bit in the DER is set.
All bits are cleared to zero following reset.
Table 21-26 Breakpoint Counter B Value and Control Register (COUNTB)
17
/
1
0
Name
CNTV
CNTC
MPC556
—
18
2
0
Counter preset value
Reserved
Counter source select
00 = not active (reset value)
01 = I-bus second watchpoint
10 = L-bus second watchpoint
11 = Reserved
19
3
0
Freescale Semiconductor, Inc.
20
4
0
For More Information On This Product,
21
5
0
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
RESERVED
22
6
0
RESET: UNAFFECTED
23
7
0
CNTV
24
8
0
Description
25
9
0
10
26
0
11
27
0
12
28
0
13
29
0
MOTOROLA
SPR 151
14
30
0
CNTC
21-53
15
31
0