MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 697

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.1 Overview
21.2 Program Flow Tracking
MPC555 / MPC556
USER’S MANUAL
The visibility and controllability requirements of emulators and bus analyzers are in op-
position to the trend of modern microcomputers and microprocessors where many bus
cycles are directed to internal resources and are not visible externally.
In order to enhance the development tool visibility and controllability, some of the de-
velopment support functions are implemented in silicon. These functions include pro-
gram flow tracking, internal watchpoint, breakpoint generation, and emulation while in
debug mode.
This section covers program flow tracking support, breakpoint/watchpoint support, de-
velopment system interface support (debug mode) and software monitor debugger
support. These features allow the user to efficiently debug systems based on the
MPC555 / MPC556.
The mechanism described below allows tracking of program instruction flow with al-
most no performance degradation. The information provided may be compressed and
captured externally and then parsed by a post-processing program using the microar-
chitecture defined below.
The program instructions flow is visible on the external bus when the MPC555 /
MPC556 is programmed to operate in serial mode and show all fetch cycles on the ex-
ternal bus. This mode is selected by programming the ISCT_SER (instruction fetch
show cycle control) field in the I-bus support control register (ICTRL), as shown in
ble
appear on the external bus. Processor performance is, therefore, much lower than
when working in regular mode.
These features, together with the fact that most fetch cycles are performed internally
(e.g., from the I-cache), increase performance but make it very difficult to provide the
user with the real program trace.
In order to reconstruct a program trace, the program code and the following additional
information from the MCU are needed:
• A description of the last fetched instruction (stall, sequential, branch not taken,
• The addresses of the targets of all indirect flow change. Indirect flow changes in-
21-21. In this mode, the processor is fetch serialized, and all internal fetch cycles
branch direct taken, branch indirect taken, exception taken)
clude all branches using the link and count registers as the target address, all ex-
ceptions, and rfi, mtmsr and mtspr (to some registers) because they may cause
a context switch.
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
SECTION 21
MOTOROLA
21-1
Ta-