MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 393

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.5.3 L-bus Memory Access Violations
11.6 Reservation Support
11.6.1 The Reservation Protocol
11.6.2 L2U Reservation Support
MPC555
USER’S MANUAL
All L-bus slaves have their own access protection logic. For consistency, all storage
access violations have the same termination result. Thus access violations for load/
store accesses started by the RCPU always have the same termination from all
slaves: assertion of the data storage exception. All other L-bus masters cause ma-
chine check exceptions.
The RCPU storage reservation protocol supports a multi-level bus structure. For each
local bus, storage reservation is handled by the local reservation logic. The protocol
tries to optimize reservation cancellation such that a PowerPC processor (RCPU) is
notified of storage reservation loss on a remote bus (U-bus, IMB or external bus) only
when it has issued a stwcx cycle to that address. That is, the reservation loss indica-
tion comes as part of the stwcx cycle.
The reservation protocol operates under the following assumptions:
The L2U is responsible for handling the effects of reservations on the L-bus and the
U-bus. For the L-bus and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
The unit for reservation is one word. A byte or half-word store request by another mas-
ter will clear the reservation flag.
A load-with-reservation request by the CPU updates the reservation address related
to a previous load-with-reservation request and sets the reservation flag for the new
location. A store-with-reservation request by the CPU clears the reservation flag. A
store request by the CPU does not clear the flag. A store request by some other master
to the reservation address clears the reservation flag.
• Each processor has at most 1 reservation flag
• A lwarx instruction sets the reservation flag
• Another lwarx instruction by same processor clears the reservation flag related
• A stwcx instruction by same processor clears the reservation flag
• A store instruction by same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to an address with an existing
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify
• Snoops accesses to all L-bus and U-bus slaves
• Holds one reservation (address) for the core
• Sets the reservation flag when the CPU issues a load-with-reservation request
/
to a previous lwarx instruction and sets again the reservation flag
reservation clears the reservation flag
the storage
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
11-7