MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 184

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

4.3.5 Compressed Code Address Format
MPC555
USER’S MANUAL
The format of the compressed code in memory requires special addressing. The
Decompressor module is responsible for generating compressed code addresses.
The compressed instruction stream may start on any of the 32 bits. Thus, five bits are
needed to locate such instruction inside a memory word. The instruction address in
“Decompression ON” mode consists of a 20-bit word pointer for the base address, bits
20 and 21 to show the relation between the left and right streams, and two 5-bit instruc-
tion pointers. This is known as the two-pointer address form. See
The base address contains the lowest word address of physical memory where the in-
struction resides.
The “left / right” bit, bit number 20, indicates which instruction stream side (left or right)
resides in the memory word location being pointed to by the base address. A zero “0”
for bit 20 will indicate that the left side is resident in the base address location. A one
“1” for bit 20 will indicate that the right side is resident in the base address location.
The instruction stream side not pointed to will reside in the following address location.
The “same line” bit, bit 21, reflects the relative location of the two side streams for the
instruction. If bit 21 is zero “0”, both left and right streams are located at the base ad-
dress location. In this case, bit 20 has no meaning and is a “don’t care” value of X. If
bit 21 is one “1”, then the two parts of the instruction are located in different address
word locations (one at “x” base address, the other at “x+4”).
Figure 4-8
Base Address
Compressed
Instruction
Address
/
MPC556
- Compressed Instruction
illustrates the three possible cases for bits 20 and 21.
x+4
x+8
x+c
x
Figure 4-7 Compressed Address Format
Freescale Semiconductor, Inc.
For More Information On This Product,
0
Go to: www.freescale.com
Rev. 15 October 2000
Word Pointer - Base Address
BURST BUFFER
:
Memory Layout
“Same Line” Bit
“Left / Right” Bit
Right Pointer Start Bit
19
1 1
22
Left
Pointer
Figure
26 27
Right
Pointer
4-7.
MOTOROLA
31
4-8