MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 621

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

17.2.5 Host Interface
17.2.6 Parameter RAM
17.3 TPU Operation
17.3.1 Event Timing
17.3.2 Channel Orthogonality
MPC555
USER’S MANUAL
The host interface registers allow communication between the CPU and the TPU3,
both before and during execution of a time function. The registers are accessible from
the IMB through the TPU3 bus interface unit. Refer to
register bit/field definitions and address mapping.
Parameter RAM occupies 256 bytes at the top of the system address map. Channel
parameters are organized as 128 16-bit words. Channels zero through 15 each have
eight parameters. The parameter RAM address map in
RAM
The CPU specifies function parameters by writing to the appropriate RAM address.
The TPU3 reads the RAM to determine channel operation. The TPU3 can also store
information to be read by the CPU in the parameter RAM. Detailed descriptions of the
parameters required by each time function are beyond the scope of this manual. Refer
to the
age (TPULITPAK/D)
All TPU3 functions are related to one of the two 16-bit time bases. Functions are syn-
thesized by combining sequences of match events and capture events. Because the
primitives are implemented in hardware, the TPU3 can determine precisely when a
match or capture event occurs, and respond rapidly. An event register for each chan-
nel provides for simultaneous match/capture event occurrences on all channels.
When a match or input capture event requiring service occurs, the affected channel
generates a service request to the scheduler. The scheduler determines the priority of
the request and assigns the channel to the microengine at the first available time. The
microengine performs the function defined by the content of the control store or emu-
lation RAM, using parameters from the parameter RAM.
Match and capture events are handled by independent channel hardware. This pro-
vides an event accuracy of one time-base clock period, regardless of the number of
channels that are active. An event normally causes a channel to request service. The
time needed to respond to and service an event is determined by which channels and
the number of channels requesting service, the relative priorities of the channels re-
questing service, and the microcode execution time of the active functions. Worst-
case event service time (latency) determines TPU3 performance in a given applica-
tion. Latency can be closely estimated. For more information, refer to the
ence Manual
Most timer systems are limited by the fixed number of functions assigned to each pin.
All TPU3 channels contain identical hardware and are functionally equivalent in oper-
/
shows how parameter words are organized in memory.
MPC556
TPU Reference Manual (TPURM/AD)
(TPURM/AD).
Freescale Semiconductor, Inc.
for more information.
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
and the Motorola
17.4 Programming Model
17.4.18 TPU3 Parameter
TPU Literature Pack-
TPU Refer-
MOTOROLA
17-3
for