MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 750

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
ECR — Exception Cause Register
Bit(s)
11:12
22:27
16
4:5
10
13
14
15
16
17
18
19
20
21
0
0
0
0
0
0
1
2
3
6
7
8
9
RESET:
RESET:
SEE
RST
17
0
/
1
0
DTLBER
ITLBER
CHSTP
FPUVE
FPASE
Name
DECE
MPC556
SYSE
MCE
EXTI
RST
PRE
SEE
ALE
TR
—
—
—
—
—
—
—
CHST
SERV
RE-
ED
18
P
2
0
0
Reserved
Reset interrupt bit. This bit is set when the system reset pin is asserted.
Checkstop bit. Set when the processor enters checkstop state.
Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
Reserved
External interrupt bit. Set when the external interrupt is asserted.
Alignment exception bit. Set when the alignment exception is asserted.
Program exception bit. Set when the program exception is asserted.
Floating point unavailable exception bit. Set when the program exception is asserted.
Decrementer exception bit. Set when the decrementer exception is asserted.
Reserved
System call exception bit. Set when the system call exception is asserted.
Trace exception bit. Set when in single-step mode or when in branch trace mode.
Floating point assist exception bit. Set when the floating point assist exception occurs.
Reserved
Software emulation exception. Set when the software emulation exception is asserted.
Reserved
Implementation specific instruction protection error
This bit is set as a result of an instruction protection error. Results in debug mode entry if debug
mode is enabled and the corresponding enable bit is set.
Reserved
Implementation specific data protection error
This bit is set as a result of an data protection error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
Reserved
MCE
BER
ITL-
19
3
0
0
SERV
Freescale Semiconductor, Inc.
RESERVED
RE-
ED
20
4
0
0
For More Information On This Product,
Table 21-27 ECR Bit Descriptions
DTL-
BER
21
5
0
0
DEVELOPMENT SUPPORT
Go to: www.freescale.com
EXTI
Rev. 15 October 2000
22
6
0
0
ALE
23
7
0
0
PRE
RESERVED
24
8
0
0
Description
FPUV
25
E
9
0
0
DECE
10
26
0
0
RESERVED
11
27
0
0
LBRK
12
28
0
0
SYSE
IBRK
13
29
0
0
MOTOROLA
EBRK
SPR 148
TR
14
30
0
D
0
FPAS
21-54
DPI
15
31
E
0
0