MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 636

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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HSRR1 — Host Service Request Register 1
17.4.10 Channel Priority Registers
CPR0 — Channel Priority Register 0
CPR1 — Channel Priority Register 1
MPC555
USER’S MANUAL
MSB
MSB
MSB
CH[15:0]
CH[15:0]
0
0
0
0
0
0
RESET:
RESET:
RESET:
Name
Name
The channel priority registers (CPR1, CPR2) assign one of three priority levels to a
channel or disable the channel.
CH 15
CH 7
CH 7
1
0
1
0
1
0
/
MPC556
Encoded type of host service. The host service request field selects the type of host service request for
the time function selected on a given channel. The meaning of the host service request bits depends
on the time function specified.
A host service request field cleared to 0b00 signals the host that service is completed by the mi-
croengine on that channel. The host can request service on a channel by writing the corresponding host
service request field to one of three non-zero states. The CPU must monitor the host service request
register until the TPU3 clears the service request to 0b00 before any parameters are changed or a new
service request is issued to the channel.
Encoded channel priority levels.
channel priority encoding.
2
0
2
0
2
0
CH 14
CH 6
CH 6
3
0
3
0
3
0
Freescale Semiconductor, Inc.
4
0
4
0
4
0
Table 17-13 HSSRx Bit Descriptions
For More Information On This Product,
Table 17-14 CPRx Bit Descriptions
CH 13
CH 5
CH 5
5
0
5
0
5
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
Rev. 15 October 2000
6
0
6
0
6
0
Table 17-15
CH 12
CH 4
CH 4
7
0
7
0
7
0
Description
Description
indicates the number of time slots guaranteed for each
8
0
8
0
8
0
CH 11
CH 3
CH 3
9
0
9
0
9
0
10
10
10
0
0
0
CH 10
CH 2
CH 2
11
11
11
0
0
0
12
12
12
0
0
0
CH 1
CH 9
CH 1
13
13
13
0
0
0
0x30 401A
0x30 441A
0x30 401C
0x30 441C
0x30 401E
0x30 441E
MOTOROLA
14
14
14
0
0
0
CH 0
CH 8
CH 0
17-18
LSB
LSB
LSB
15
15
15
0
0
0

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