MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 497

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.5.3 Delay Before Transfer
14.7.5.4 Delay After Transfer
MPC555
USER’S MANUAL
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state. At reset, the SCK baud rate is initialized to one eighth
of the IMB clock frequency.
Table 14-21
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or
user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of
the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined
delay before the assertion of SCK. The following expression determines the actual de-
lay before SCK:
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the SCK period.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. Writing a value to the DTL field in SPCR1 specifies a delay period.
The DT bit in each command RAM byte determines whether the standard delay period
/
MPC556
Table 14-21 Example SCK Frequencies with a 40-MHz IMB Clock
where DSCKL is in the range from 1 to 127.
A zero value for DSCKL causes a delay of 128 IMB clocks, which
equals 3.2 µs for a 40-MHz IMB clock. Because of design limits, a
DSCKL value of one defaults to the same timing as a value of two.
provides some example SCK baud rates with a 40-MHz IMB clock.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
Division Ratio
For More Information On This Product,
280
510
14
28
58
4
6
8
Go to: www.freescale.com
Rev. 15 October 2000
PCS to SCK Delay
SPBR Value
140
255
14
29
2
3
4
7
NOTE
=
DSCKL
------------------- -
f SYS
Frequency
10.00 MHz
78.43 kHz
6.67 MHz
5.00 MHz
2.86 MHz
1.43 MHz
689 kHz
143 kHz
SCK
MOTOROLA
14-35