MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 648

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MISRH — Multiple Input Signature Register High
MISRL — Multiple Input Signature Register Low
MISCNT — MISC Counter
RESET:
RESET:
RESET:
18.3.5 MISC Counter (MISCNT)
18.4 Operation
18.4.1 Normal Operation
18.4.2 Standby Operation
MPC555
USER’S MANUAL
MSB
MSB
D31
D15
0
0
0
0
The MISCNT contains the address of the current MISC memory access. This registers
is read-only. Note that the naming of the A[31:0] bits represents little-endian bit encod-
ing.
Exiting TPU3 emulation mode or clearing the MISEN bit in the DPTMCR results in the
reset of this register.
The DPTRAM module has several modes of operation. The following sections de-
scribe DPTRAM operation in each of these modes.
In normal operation, the DPTRAM is powered by V
IMB3 by a bus master.
Read or write accesses of 8, 16, or 32 bits are supported. In normal operation, neither
TPU3 accesses the array, nor do they have any effect on the operation of the DP-
TRAM module.
The DPTRAM array uses a separate power supply VDDSRAM to maintain the con-
tents of the DPTRAM array during a power-down phase.
When the RAM array is powered by the VDDSRAM pin of the MCU, access to the RAM
array is blocked. Data read from the RAM array during this condition cannot be guar-
anteed. Data written to the DPTRAM may be corrupted if switching occurs during a
write operation.
RESERVED
D30
D14
1
0
1
0
/
MPC556
D29
D13
2
0
2
0
A12
D28
D12
3
0
3
0
A11
Freescale Semiconductor, Inc.
D27
D11
4
0
4
0
For More Information On This Product,
A10
D26
D10
DUAL-PORT TPU RAM (DPTRAM)
5
0
5
0
Go to: www.freescale.com
Rev. 15 October 2000
D25
A9
D9
6
0
6
0
Last Memory Address
D24
A8
D8
7
0
7
0
D23
A7
D7
8
0
8
0
D22
A6
D6
9
0
9
0
DDL
D21
A5
10
D5
10
0
0
and may be accessed via the
D20
A4
11
D4
11
0
0
D19
12
A3
D3
12
0
0
D18
A2
13
D2
13
0
0
0x30 0006
0x30 0008
0x30 000A
MOTOROLA
D17
14
A1
D1
14
0
0
LSB
18-6
D16
LSB
A0
15
D0
15
0
0