MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 416

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.3.2 Port B Pin Functions
13.3.2.1 Port B Analog Input Pins
13.3.2.2 Port B Digital Input Pins
13.3.3 External Trigger Input Pins
13.3.4 Multiplexed Address Output Pins
MPC555
USER’S MANUAL
Port A pins are connected to a digital input synchronizer during reads and may be used
as general purpose digital inputs. Since port A read captures the data on all pins, in-
cluding those used for digital outputs or analog inputs, the user should employ a
“masking” operation to filter the inappropriate bits from the input byte.
Each port A pin is configured as an input or output by programming the port data
direction register (DDRQA). Digital input signal states are read into the PORTQA data
register when DDRQA specifies that the pins are inputs. Digital data in PORTQA is
driven onto the port A pins when the corresponding bits in DDRQA specify outputs.
The eight port B pins can be used as analog inputs, or as an 8-bit digital input-only port.
Refer to the following paragraphs for more information.
When used as analog inputs, the eight port B pins are referred to as AN[51:48]/
AN[3:0]. Since port B functions as analog and digital input-only, the analog character-
istics are different from those of port A. All of the analog signal input pins may be used
for at least one other purpose.
Port B pins are referred to as PQB[7:0] when used as an 8-bit digital input-only port.
In addition to functioning as analog input pins, the port B pins are also connected to
the input of a synchronizer during reads and may be used as general-purpose digital
inputs.
Since port B pins are input-only, there is no associated data direction register. Digital
input signal states are read from the PORTQB data register. Since a port B read cap-
tures the data on all pins, including those used for analog inputs, the user should em-
ploy a “masking” operation to filter the inappropriate bits from the input byte.
The QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trig-
ger pins is associated with one of the scan queues. When a queue is in external trigger
mode, the corresponding external trigger pin is configured as a digital input.
In non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer
which routes the analog signals into the A/D converter.
In externally multiplexed mode, the QADC64 allows automatic channel selection
through up to four external 1-of-8 multiplexer chips. The QADC64 provides a 3-bit mul-
tiplexed address output to the external multiplexer chips to allow selection of one of
eight inputs. The multiplexed address output signals MA[2:0] can be used as multiplex
address output bits or as general-purpose I/O.
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
13-4