MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 756

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

22.2 JTAG Signal Descriptions
MPC555
USER’S MANUAL
The MPC555 / MPC556 has five dedicated JTAG pins, which are described in
22-1. The TDI and TDO scan ports are used to scan instructions as well as data into
the various scan registers for JTAG operations. The scan operation is controlled by the
test access port (TAP) controller, which in turn is controlled by the TMS input se-
quence.
To enable JTAG on reset for board test, bit 11 (DGPC select JTAG pins) and bit 16
(PRPM peripheral mode enable) of the reset configuration word should be held high
during the rising edge of reset (see
need to be configurable on the user board to allow JTAG test of a board. To allow nor-
mal operation of the board these bits need to be low in the reset configuration word.
/
MPC556
TCK
TMS
TDI
Freescale Semiconductor, Inc.
Figure 22-2 Test Logic Block Diagram
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
For More Information On This Product,
JCOMP
Instruction apply & decode register
TAP CONTROLLER
3
Bypass
4-bit Instruction register
Boundary scan register
Go to: www.freescale.com
2
Rev. 15 October 2000
1
7.5.2 Hard Reset Configuration
0
TRST
M
U
X
M
U
X
TDO
Word). These
MOTOROLA
Table
22-2