MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 518

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.8.7.7 Receiver Functional Operation
MPC555
USER’S MANUAL
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The re-
ceiver contains a receive serial shifter and a parallel receive data register (RDRx) lo-
cated in the SCI data register (SCxDR). The serial shifter cannot be directly accessed
by the CPU. The receiver is double-buffered, allowing data to be held in the RDRx
while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for
each bit-time. This state machine controls when the bit processor logic is to sample
the RXD pin and also controls when data is to be passed to the receive serial shifter.
A receive time clock is used to control sampling and synchronization. Data is shifted
into the receive serial shifter according to the most recent synchronization of the re-
ceive time clock with the incoming data stream. From this point on, data movement is
synchronized with the MCU IMB clock. Operation of the receiver state machine is de-
tailed in the
The number of bits shifted in by the receiver depends on the serial format. However,
all frames must end with at least one stop bit. When the stop bit is received, the frame
is considered to be complete, and the received data in the serial shifter is transferred
to the RDRx. The receiver data register flag (RDRF) is set when the data is trans-
ferred.
The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE
flag in SCxSR is set. A framing error is usually caused by mismatched baud rates be-
tween the receiver and transmitter or by a significant burst of noise. Note that a framing
error is not always detected; the data in the expected stop bit-time may happen to be
a logic one.
Noise errors, parity errors, and framing errors can be detected while a data stream is
being received. Although error conditions are detected as bits are received, the noise
/
1
R
T
1
*
* Restart RT Clock
MPC556
1 1 1
R
T
1
* *
R
T
1
Queued Serial Module Reference Manual
R
T
1
* *
R
T
1
1
1
R
T
1
* *
1 1 1
R
T
1
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Figure 14-14 Start Search Example
R
T
1
* *
R
T
1
R
T
1
0
Go to: www.freescale.com
R
T
2
Rev. 15 October 2000
0
R
T
3
R
T
4
Perceived Start Bit
0
R
T
5
Actual Start Bit
R
T
6
0 0 0 0
R
T
7
R
T
8
R
T
9
R
T
1
0 1 2 3 4 5 6
R
T
1
R
T
1
(QSMRM/AD).
R
T
1
R
T
1
R
T
1
R
T
1
*
R
T
1
R
T
2
R
T
3
LSB
MOTOROLA
14-56