MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 484

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.2.1 Receive RAM
14.7.2.2 Transmit RAM
14.7.2.3 Command RAM
MPC555
USER’S MANUAL
Data received by the QSPI is stored in this segment, to be read by the CPU. Data
stored in the receive RAM is right-justified,( i.e., the least significant bit is always in the
right-most bit position within the word regardless of the serial transfer length). Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, half-word, or word ad-
dressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed. If
the corresponding peripheral, such as a serial input port, is used solely to input data,
then this segment does not need to be initialized.
Data must be written to transmit RAM in a right-justified format. The QSPI cannot mod-
ify information in the transmit RAM. The QSPI copies the information to its data serial-
izer for transmission. Information remains in transmit RAM until overwritten.
Command RAM is used by the QSPI in master mode. The CPU writes one byte of con-
trol information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 32 bytes. Each byte is divided into two fields. The periph-
eral chip-select field, enables peripherals for transfer. The command control field pro-
vides transfer options.
0x30 517F
0x30 5140
/
MPC556
Half-Word
Receive
RAM
RRD
RRE
RR1
RR2
RRF
RR0
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Figure 14-5 QSPI RAM
0x30 51BF
Go to: www.freescale.com
0x30 5180
Rev. 15 October 2000
Half-Word
Transmit
RAM
TRD
TRE
TR0
TR1
TR2
TRF
0x30 51DF
0x30 51C0
Command
RAM
CRD
CRE
CRF
CR0
CR1
CR2
Byte
MOTOROLA
14-22