MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 510

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
Bit(s)
0:6
10
11
12
7
8
9
/
MPC556
RDRF
Name
TDRE
IDLE
RAF
OR
TC
—
Transmit data register empty. TDRE is set when the byte in TDRx is transferred to the transmit
serial shifter. If this bit is zero, the transfer is yet to occur and a write to TDRx will overwrite the
previous value. New data is not transmitted if TDRx is written without first clearing TDRE.
0 = Transmit data register still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to the transmit data register.
For transmit queue operation, this bit should be ignored by software.
Transmit complete. TC is set when the transmitter finishes shifting out all data, queued pream-
bles (mark/idle-line), or queued breaks (logic zero).
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
For transmit queue operation, TC is cleared when SCxSR is read with TC set, followed by a write
to SCTQ[0:15].
Receive data register full. RDRF is set when the contents of the receive serial shifter are trans-
ferred to register RDRx. If one or more errors are detected in the received word, the appropriate
flag(s) (NF, FE, or PF) are set within the same clock cycle.
0 = Receive data register is empty or contains previously read data.
1 = Receive data register contains new data.
For receiver queue operation, this bit should be ignored by software.
Receiver active flag. RAF indicates whether the receiver is busy. This flag is set when the receiv-
er detects a possible start bit and is cleared when the chosen type of idle line is detected. RAF
can be used to reduce collisions in systems with multiple masters.
0 = SCI receiver is idle.
1 = SCI receiver is busy.
Idle line detected. IDLE is set when the receiver detects an idle-line condition (reception of a min-
imum of 10 or 11 consecutive ones as specified by ILT in SCCxR1). This bit is not set by the idle-
line condition when RWU in SCCxR1 is set. Once cleared, IDLE is not set again until after RDRF
is set (after the line is active and becomes idle again). If a break is received, RDRF is set, allow-
ing a subsequent idle line to be detected again.
Under certain conditions, the IDLE flag may be set immediately following the negation of RE in
SCCxR1. System designs should ensure this causes no detrimental effects.
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a
read of SCRQ[0:15].
Overrun error. OR is set when a new byte is ready to be transferred from the receive serial shifter
to register RDRx, and RDRx is already full (RDRF is still set). Data transfer is inhibited until OR
is cleared. Previous data in RDRx remains valid, but additional data received during an overrun
condition (including the byte that set OR) is lost.
Note that whereas the other receiver status flags (NF, FE, and PF) reflect the status of data al-
ready transferred to RDRx, the OR flag reflects an operational condition that resulted in a loss of
data to RDRx.
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
Reserved
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-25 SCxSR Bit Descriptions
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Description
MOTOROLA
14-48