MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 404

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.2 UIMB Block Diagram
12.3 Clock Module
MPC555
USER’S MANUAL
The clock module within the UIMB interface generates the IMB clock. The IMB clock
is the main timing reference used within the IMB modules. The IMB clock is often re-
ferred to in the IMB module sections as F
The IMB clock is generated based on the STOP and HSPEED bits in the UIMB module
configuration register (UMCR). If the STOP bit is 1, the IMB clock is not generated. If
the STOP bit is 0 and the HSPEED bit is 0, the IMB clock is generated as the inversion
of the internal system clock. This is the same frequency as the CLKOUT if EBDF is
0b00 – full speed external bus. (See
clock is one-half of the internal system frequency. (See
/
MPC556
STOP
0
0
1
Figure 12-1 UIMB Interface Module Block Diagram
Table 12-1 STOP and HSPEED Bit Functionality
U-bus
Freescale Semiconductor, Inc.
HSPEED
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
0
1
X
Go to: www.freescale.com
Rev. 15 October 2000
IMB bus frequency is the same as U-bus frequency.
IMB bus frequency is half that of the U-bus frequency.
IMB clock is not generated.
Address
Decode
Interface
U-bus
Data
Mux
Figure
Clock Control
Synchronizer
Scan Control
Interrupt
SYS
12-2.) If the HSPEED bit is 1, then the IMB
or IMB3 clock.
Interface
IMB3
Functionality
Figure
12-3.)
IMB3
MOTOROLA
12-2