MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 438

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
(FROM CONTROL REGISTER 0):
PRESCALER RATE SELECTION
IMB CLOCK (F
To accommodate wide variations of the main MCU clock frequency (IMB clock —
F
clock to a frequency within the specified QCLK tolerance range. To allow the A/D con-
version time to be maximized across the spectrum of IMB clock frequencies, the
QADC64 prescaler permits the frequency of QCLK to be software selectable. It also
allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK
with the prescaler clock low time (PSL) field. The combination of the PSH and PSL pa-
rameters establishes the frequency of the QCLK.
SYS
Queue 1 & 2 TIMER MODE RATE SELECTION
HIGH TIME CYCLES (PSH)
LOW TIME CYCLES (PSL)
ADD HALF CYCLE TO HIGH (PSA)
INPUT SAMPLE TIME (FROM CCW)
/
), QCLK is generated by a programmable prescaler which divides the MCU IMB
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
SYS
)
Figure 13-8 QADC64 Clock Subsystem Functions
5
Freescale Semiconductor, Inc.
DOWN COUNTER
8
For More Information On This Product,
ONE'S COMPLEMENT
5-BIT
COMPARE
2
3
DETECT
ZERO
5
3
Go to: www.freescale.com
Rev. 15 October 2000
2 7
2 8
LOAD PSH
2 9
2 10
PERIODIC/INTERVAL
BINARY COUNTER
A/D CONVERTER
STATE MACHINE
TIMER SELECT
2 11
2 12
2 13
2 14
RESET QCLK
SET QCLK
2 15
2 16 2 17
( F
GENERATE
SYS
QADC64 CLOCK
CLOCK
10
/ ÷2 TO F
2
SYS
/÷40 )
SAR CONTROL
SAR
PERIODIC/INTERVAL
TRIGGER EVENT
FOR Q1 AND Q2
QCLK
MOTOROLA
13-26