MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 409

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

UMCR — UIMB Module Configuration Register
12.5 Programming Model
12.5.1 UIMB Module Configuration Register (UMCR)
MPC555
USER’S MANUAL
STOP
MSB
HRESET:
0
0
16
HRESET:
0
Table 12-5
address offset shown in this table is from the start of the block reserved for UIMB reg-
isters. As shown in
gins at offset 0x30 7F80 from the start of the MPC555 / MPC556 internal memory map
(the last 128-byte sub-block of the UIMB interface memory map).
Any word, half-word or byte access to a 32-bit location within the UIMB interface reg-
ister decode block that is unimplemented (defined as reserved) causes the UIMB in-
terface to asserting a data error exception on the U-bus.The entire 32-bit location must
be defined as reserved in order for a data error exception to be asserted.
Unimplemented bits in a register return zero when read.
The UIMB module configuration register (UMCR) is accessible in supervisor mode
only.
1
0
IRQMUX
17
/
0
MPC556
NOTES:
Access
S/T
1. S = Supervisor mode only, T = Test mode only
S
—
—
2
0
S
18
0
1
lists the registers used for configuring and testing the UIMB module. The
HSPEE
19
0x30 7F80
0x30 7F84 —
0x30 7F8C
0x30 7F90
0x30 7F94 —
0x30 7F9C
0x30 7FA0
D
3
1
0
Figure 1-3
Base Address
Table 12-5 UIMB Interface Register Map
Freescale Semiconductor, Inc.
20
0
For More Information On This Product,
4
0
U-BUS TO IMB3 BUS INTERFACE (UIMB)
21
0
5
0
Go to: www.freescale.com
in
Rev. 15 October 2000
22
0
1.3 MPC555 / MPC556 Address
6
0
UIMB Module Configuration Register (UMCR)
See
Reserved
UIMB Test Control Register (UTSTCREG)
Reserved
Reserved
Interrupt Request Pending (UIPEND)
See
(UIPEND)
RESERVED
23
0
7
0
Table 12-6
12.5.3 Pending Interrupt Request Register
24
0
for bit descriptions.
8
0
for bit descriptions.
25
RESERVED
0
9
0
Register
26
0
10
0
27
0
11
0
28
0
12
0
Map, this block be-
29
0
13
0
0x30 7F80
MOTOROLA
30
0
14
0
LSB
31
12-7
0
15
0