MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 857

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

D.17 Read / Write Timers and Pin TPU Function (RWTPIN)
MPC555 / MPC556
USER’S MANUAL
The RWTPIN TPU function enables the CPU to read both the TCR1 and TCR2 timer
counters via locations in PRAM and selectively load TCR1 or TCR2 with a CPU sup-
plied value contained in PRAM. The function also allows control of the pin state and
direction of the RWTPIN channel.
A pin state parameter is maintained in PRAM and is updated upon every service
request. It can contain a value of the current pinstate whether the pin is programmed
as an input or output.
The function also receives links, and upon receipt will read the two TCRs into PRAM,
updating the pinstate parameter. A maskable interrupt request to the CPU is
generated.
The CPU can control the channel pin, the channel pin and the TCRs, or just the TCRs.
To control the pin only, the ‘read TCR’ option is used and the values returned ignored.
Controlling the TCRs without effect on the pin allows this function to be run on a TPU
channel whose pin is being controlled by a different function running on another chan-
nel (e.g., a slave stepper motor channel). See Motorola TPU Progamming Note
The TPU Function Library And TPU Emulation Mode, (TPUPN00/D).
Figure D-27
shows all of the host interface areas for the PTA function.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TPU ROM FUNCTIONS
Rev. 15 October 2000
MOTOROLA
Using
D-43