MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 686

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
the value of the NVM fuse. Reading CENSOR[0:1] while setting or clearing with the
high voltage applied (CSC = 1 and EHV = 1) will return zeroes.
The set operation changes the state in an NVM fuse from a zero to a one by program-
ming NVM bit 0 and erasing NVM bit 1 simultaneously in the NVM fuse. This set oper-
ation can be performed without changing the contents of the CMF array.
To set one or both of the bits in CENSOR[0:1],
The clear operation changes the state in an NVM fuse from a one to a zero by erasing
NVM bit 0 and programming NVM bit 1 simultaneously in the NVM fuse. This clear op-
eration can be done only while erasing the entire CMF array and shadow information.
To clear CENSOR[0:1],
1. Using section
2. Write a one to the CENSOR bit(s) to be set.
3. Write EHV = 1 in the CMFCTL register. This will apply the programming voltag-
4. Read the CMFCTL register until HVS = 0.
5. Write EHV = 0 in the CMFCTL register.
6. Read the CMFMCR CENSOR bit(s) that are being set. If any bit selected for set
7. Write SES = 0 and CSC = 0.
1. Write PROTECT[0:7] = 0x00 to enable the entire array for erasure.
2. Using section
3. Perform an erase interlock write.
4. Write EHV = 1 in the CMFCTL register. This will apply the erase voltages to the
5. Read the CMFCTL register until HVS = 0.
6. Write EHV = 0 in the CMFCTL register.
7. Read the entire CMF array and the shadow information words. If any bit equals
8. Read CENSOR[0:1]. If CENSOR[0:1]
9. Write SES = 0 and CSC = 0.
/
Programmed
Programmed
MPC556
NVM bit 0
CLKPM, write the pulse width timing control fields for an erase pulse, CSC = 1,
PE = 0 and SES = 1 in the CMFCTL register.
es to NVM bit 0 and the erase voltages to NVM bit 1 simultaneously.
is a 0 go to step 3.
CLKPM, write the pulse width timing control fields for an erase pulse,
BLOCK[0:7] = 0xFF, CSC = 1, PE = 1 and SES = 1 in the CMFCTL register.
entire CMF array and NVM bit 0 and the programming voltages to NVM bit 1
simultaneously.
zero, go to step 4.
Erased
Erased
Freescale Semiconductor, Inc.
For More Information On This Product,
19.7.6 A Technique to Determine SCLKR, CLKPE, and
19.7.6 A Technique to Determine SCLKR, CLKPE, and
Table 19-17 NVM Fuse States
CDR MoneT FLASH EEPROM
Go to: www.freescale.com
Rev. 15 October 2000
Programmed
Programmed
NVM bit 1
Erased
Erased
≠
0 go to step 4.
NVM Fuse Bit Value
Cleared (0)
Undefined
Undefined
Set (1)
MOTOROLA
19-34