MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 568

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.14.1 MIOS Interrupt Request Submodule (MIRSM)
MPC555
USER’S MANUAL
The MIOS interrupt request submodule gathers service request flags from each group
of up to 16 submodules and transfers those requests to the MIOS1 interrupt control
section (ICS).
Each submodule that is capable of generating an interrupt can assert a flag line when
an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two
MIRSMs are needed.
• The MIOS interrupt request submodules (MIRSM).
/
IMB3
MPC556
Level n
RQSM #0
Submodules 16 to 23
Figure 15-8
IRQ Pend. Register
Status Register
Enable Register
RQSM #1
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
Figure 15-8 MIOS Interrupt Structure
For More Information On This Product,
(Flags)
shows a block diagram of the interrupt architecture.
Go to: www.freescale.com
Rev. 15 October 2000
Acknowledge
Request
MBISM
Interrupt Control Section
Submodule 13
Submodule 2
IRQ Level Register
MOTOROLA
15-32