MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 523

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QSCI1SR — QSCI1 Status Register
14.9.2.2 QSCI1 Status Register
14.9.3 QSCI1 Transmitter Block Diagram
MPC555
USER’S MANUAL
RESET:
Bit(s)
12:15
MSB
8:11
0:2
0
0
3
4
5
6
7
The block diagram of the enhancements to the SCI transmitter is shown in
15.
RESERVED
/
QRPNT
QPEND
1
0
MPC556
QBHF
QTHE
QBHE
Name
QTHF
QOR
—
2
0
Reserved
Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred
from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data
transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid.
Additional data received during a queue overrun condition is not lost provided the receive queue
is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received
in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the
OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
0 = The queue is empty before valid data is in the SC1DR
1 = The queue is not empty when valid data is in the SC1DR
Receiver queue top-half full. QTHF is set when the receive queue locations SCRQ[0:7] are com-
pletely filled with new data received via the serial shifter. QTHF is cleared when register
QSCI1SR is read with QTHF set, followed by a write of QTHF to zero.
0 = The queue locations SCRQ[0:7] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[0:7] are completely full of newly received data
Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are
completely filled with new data received via the serial shifter. QBHF is cleared when register
QSCI1SR is read with QBHF set, followed by a write of QBHF to zero.
0 = The queue locations SCRQ[8:15] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[8:15] are completely full of newly received data
Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue
locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when
register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero.
0 = The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[0:7]
Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit
queue locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared
when register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero.
0 = The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[8:15]
Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next
valid data frame will be stored within the receive queue. This field is writable in test mode only;
otherwise it is read-only.
Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in
the queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; other-
wise it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can
be specified.
QOR
3
0
Freescale Semiconductor, Inc.
Table 14-31 QSCI1SR Bit Descriptions
QTHF QBHF QTHE QBHE
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
4
1
5
1
Go to: www.freescale.com
Rev. 15 October 2000
6
1
7
1
8
0
Description
9
0
QRPNT
10
0
11
0
12
0
13
0
QPEND
0x30 502A
MOTOROLA
Figure 14-
14
0
14-61
LSB
15
0