MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 502

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.7 Slave Wraparound Mode
MPC555
USER’S MANUAL
above. Note that PCS[0]/SS does not necessarily have to be negated between trans-
fers.
Once the proper number of bits (designated by BITS) are transferred, the QSPI stores
the received data in the receive data segment, stores the internal working queue point-
er value in CPTQP, increments the internal working queue pointer, and loads the new
transmit data from the transmit data segment into the data serializer. The internal
working queue pointer address is used the next time PCS[0]/SS is asserted, unless
the CPU writes to the NEWQP first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the
QSPI does not drive the clock line nor the chip-select lines and, therefore, does not
generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The trans-
mit data is loaded into the data serializer (refer to
the PCS[0]/SS pin is pulled low the MISO pin becomes active and the serializer then
shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the
incoming SCK signal. The QSPI uses CPHA and CPOL to determine which incoming
SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin
uses to drive the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as
a match with the address in ENDQP), regardless of whether PCS[0]/SS remains se-
lected or is toggled between serial transfers. Receiving the proper number of bits caus-
es the received data to be stored. The QSPI always transmits as many bits as it
receives at each queue address, until the BITS value is reached or PCS[0]/SS is ne-
gated.
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether
wraparound mode is enabled or disabled. An optional interrupt to the CPU is gen-er-
ated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wrap-
around mode is enabled. A description of SPIFIE bit can be found in 4.3.3 QSPI
Control Register 2 (SPCR2).
In wraparound mode, the QSPI cycles through the queue continuously. Each time the
end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it re-
mains set, and the QSPI continues to send interrupt requests to the CPU (assuming
SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE.
As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately
stop the CPU interrupts, but only prevents future interrupts from this source. To clear
the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, fol-
lowed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in wrap-
around mode even while the QSPI is requesting interrupt service from the CPU. The
internal working queue pointer is incremented to the next address and the commands
are executed again. SPE is not cleared by the QSPI. New receive data overwrites pre-
viously received data located in the receive data segment.
/
MPC556
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
Figure
14-1) for transmission. When
MOTOROLA
14-40