MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 632

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

DSSR — Development Support Status Register
17.4.4 Development Support Status Register
17.4.5 TPU3 Interrupt Configuration Register
TICR — TPU3 Interrupt Configuration Register
MPC555
USER’S MANUAL
MSB
Bit(s)
13:15
MSB
0:7
0
0
10
11
12
0
RESET:
8
9
RESET:
1
1
0
/
MPC556
CHBK
Name
PCBK
SRBK
BKPT
TPUF
RESERVED
—
—
2
2
0
Reserved
Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the
TPU3 asserts the BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the
TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted.
µPC breakpoint flag. PCBK is asserted if a breakpoint occurs because of a µPC (microprogram
counter) register match with the µPC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN
register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag
is cleared.
Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the
service request latches being asserted along with their corresponding enable flag in the devel-
opment support control register. SRBK is negated when the BKPT flag is cleared.
TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE
being asserted. This flag is automatically negated when the TPU3 exits the halted state because
of FREEZE being negated.
Reserved
RESERVED
3
3
0
Freescale Semiconductor, Inc.
4
4
0
For More Information On This Product,
Table 17-8 DSSR Bit Descriptions
5
0
5
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
CIRL
Rev. 15 October 2000
6
0
6
0
7
0
7
0
BKPT PCBK CHBK SRBK TPUF
8
0
8
0
Description
ILBS
9
0
9
0
10
10
0
0
11
11
0
0
RESERVED
12
12
0
13
13
0
0x30 4006
0x30 4406
RESERVED
0x30 4008
0x30 4408
MOTOROLA
14
14
0
17-14
LSB
LSB
15
15
0