MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 354

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
chip-select for accessing the boot flash EEPROM. The chip select allows zero to 30
wait states.
Figure 10-2
Most memory controller features are common to all four banks. (For features unique
to the CS[0] bank, refer to
address decode for each memory bank is possible with 17 bits having address mask-
ing. The full 32-bit decode is available, even if all 32 address bits are not sent to the
MPC555 / MPC556 pins.
Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to
4 Gbytes. Each memory bank can be selected for read-only or read/write operation.
The access to a memory bank can be restricted to certain address type codes for sys-
tem protection. The address type comparison occurs with a mask option as well.
INTERNAL ADDRESSES [0:16, AT[0:2]
Base
Register
/
MPC556
Base Register 3 (BR3)
is a block diagram of the MPC555 / MPC556 memory controller.
Base Register (DMBR)
Figure 10-2 Memory Controller Block Diagram
Dual Mapping
Freescale Semiconductor, Inc.
For More Information On This Product,
Region Match Logic
10.4 Global (Boot) Chip-Select
0 (OR0)
Go to: www.freescale.com
MEMORY CONTROLLER
1 (OR1)
Rev. 15 October 2000
2 (OR2)
Option
Register
Wait State
Counter
Option Register 3 (OR3)
Option Register (DMOR)
Dual Mapping
Expired
Load
ATTRIBUTES
0 (OR0)
Operation.) A full 32-bit
1 (OR1)
General-Purpose
2 (OR2)
Chip-Select
Machine
(GPCM)
MOTOROLA
CS[0:3]
WE/BE[0:3]
OE
10-2