MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 650

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

18.4.5 Freeze Operation
18.4.6 TPU3 Emulation Mode Operation
18.5 Multiple Input Signature Calculator (MISC)
MPC555
USER’S MANUAL
Switching to VDDSRAM occurs if VDDL drops below its specified value when the RAM
module is in stop mode.
The DPTRAM will not enter stop mode if either or both of the TP1EMM or TP2EMM
signals are asserted, indicating TPU3 emulation mode.
The FREEZE line on the IMB3 has no effect on the DPTRAM module. When the freeze
line is set, the DPTRAM module will operate in its current mode of operation. If the DP-
TRAM module is not disabled, (RAMDS = 0), it may be accessed via the IMB3. If the
DPTRAM array is being used by the TPU in emulation mode, the DPTRAM will still be
able to be accessed by the TPU microengine.
To emulate TPU3 time functions, the user stores the microinstructions required for all
time functions to be used, in the RAM array. This must be done with the DPTRAM in
its normal operating mode and accessible from the IMB3. After the time functions are
stored in the array, the user places one or both of the TPU3 units in emulation mode.
The RAM array is then controlled by the TPU3 units and disconnected from the IMB3.
To use the DPTRAM for microcode accesses, set the EMU bit in the corresponding
TPU3 module configuration register. Through the auxiliary buses, the TPU3 units can
access word instructions simultaneously at a rate of up to 40 MHz.
When the RAM array is being used by either or both of the TPU3 units, all accesses
via the IMB3 are disabled. The control registers have no effect on the RAM array. Ac-
cesses to the array are ignored, allowing an external RAM to replace the function of
the general-purpose RAM array.
The contents of the RAM are validated using a multiple input signature calculator
(MISC). MISC reads of the RAM are performed only when the MPC555 / MPC556 is
in emulation mode and the MISC is enabled (MISEN = 1 in the DPTMCR).
Refer to
eration in emulation mode.
The integrity of the RAM data is ensured through the use of a MISC. The RAM data is
read in reverse address order and a unique 32-bit signature is generated based on the
output of these reads. MISC reads are performed when one of the TPU3 modules
does not request back-to-back accesses to the RAM provided that the MISEN bit in
the DPTMCR is set.
The MISC generates the DPTRAM signature based on the following polynomial:
/
MPC556
17.3.6 Emulation Support
Freescale Semiconductor, Inc.
For More Information On This Product,
DUAL-PORT TPU RAM (DPTRAM)
G x ( )
Go to: www.freescale.com
Rev. 15 October 2000
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MOTOROLA
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