MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 699

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.2.1.1 Instruction Queue Status Pins — VF [0:2]
MPC555
USER’S MANUAL
000
001
010
011
100
101
110
111
NOTES:
VF[0:2]
The status pins are divided into two groups and one special case listed below:
Instruction queue status pins denote the type of the last fetched instruction or how
many instructions were flushed from the instruction queue. These status pins are used
for both functions because queue flushes only happen in clocks that there is no fetch
type information to be reported.
Possible instruction types are defined in
Table 21-2
1. Unless next clock VF=111. See below.
2. The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions.
Refer to
/
MPC556
None
Sequential
Branch (direct or indirect) not taken
VSYNC was asserted/negated and therefore the
next instruction will be marked with the indirect
change-of-flow attribute
Exception taken — the target will be marked with the
indirect change-of-flow attribute
Branch indirect taken, rfi, mtmsr, isync and in some
cases mtspr to CMPA-F, ICTRL, ECR, or DER —
the target will be marked with the indirect change-of-
flow attribute
Branch direct taken
Branch (direct or indirect) not taken
21.2.3 Sequential Instructions Marked as Indirect
shows VF[0:2] encodings for instruction queue flush information.
2
Table 21-1 VF Pins Instruction Encodings
Freescale Semiconductor, Inc.
Instruction Type
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
Table
21-1.
More instruction type information
More instruction type information
More instruction type information
More instruction type information
Queue flush information
Queue flush information
Queue flush information
Queue flush information
Branch.
VF Next Clock Will Hold
1
1
1
1
MOTOROLA
21-3