MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 471

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QSPI_IL — QSPI Interrupt Level Register
14.6 QSMCM Pin Control Registers
MPC555
USER’S MANUAL
RESET:
MSB
Bit(s)
11:15
0
0
0:10
Table 14-7
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial sub-
systems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock
source.)
The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins.
Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit as-
signs the pin to the QSPI.
PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled,
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete in-
put. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx
pin is assigned its SCI function.
The port QS data direction register (DDRQS) determines whether QSPI pins are in-
puts or outputs. Clearing a bit makes the corresponding pin an input; setting a bit
makes the pin an output. DDRQS affects both QSPI function and I/O function.
14-10
/
MPC556
1
0
summarizes the effect of DDRQS bits on QSPI pin function.
ILQSPI
Name
—
2
0
lists the three QSMCM pin control registers.
0x30 5014
0x30 5016
0x30 5017
Address
3
0
Table 14-7 QSMCM Pin Control Registers
Reserved
Interrupt level of SPI
00000 = lowest interrupt level request (level 0)
11111 = highest interrupt level request (level 31)
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-6 QSPI_IL Bit Descriptions
For More Information On This Product,
4
0
RESERVED
QSMCM Port Data Register (PORTQS)
See
descriptions.
PORTQS Pin Assignment Register (PQSPAR)
See
PORTQS Data Direction Register (DDRQS)
See
5
0
Go to: www.freescale.com
Rev. 15 October 2000
14.6.1 Port QS Data Register (PORTQS)
Table 14-11
Table 14-11
6
0
7
0
for bit descriptions.
for bit descriptions.
Register
8
Description
9
10
11
for bit
12
ILQSPI
13
0x30 5006
MOTOROLA
14
Table
LSB
14-9
15