MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 735

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.5.6.7 Serial Data Out of Development Port — Trap Enable Mode
21.5.6.8 Development Port Serial Communications — Debug Mode
MPC555
USER’S MANUAL
NOTES:
Ready
(0)
(0)
(0)
(0)
The debug port command function allows the development tool to either assert or ne-
gate breakpoint requests, reset the processor, activate or deactivate the fast down-
load procedure.
In trap enable mode the only response out of the development port is “sequencing er-
ror.”
Data that can come out of the development port is shown in
from CPU” and “CPU interrupt” status cannot occur in trap enable mode.
1. The “Freeze” status is set to (1) when the CPU is in debug mode and to (0) otherwise.
2. The “Download Procedure in progress” status is asserted (0) when Debug port in the Download procedure and
When not in debug mode the sequencing error encoding indicates that the transmis-
sion from the external development tool was a debug mode transmission. When a se-
quencing error occurs the development port will ignore the data shifted in while the
sequencing error was shifting out. It will be treated as a NOP function.
Finally, the null output encoding is used to indicate that the previous transmission did
not have any associated errors.
When not in debug mode, ready will be asserted at the end of each transmission. If
debug mode is not enabled and transmission errors can be guaranteed not to occur,
the status output is not needed.
When in debug mode the development port starts communications by setting DSDO
low to indicate that the CPU is trying to read an instruction from DPIR or data from DP-
DR. When the CPU writes data to the port to be shifted out the ready bit is not set. The
port waits for the CPU to read the next instruction before asserting ready. This allows
duplex operation of the serial port while allowing the port to control all transmissions
from the external development tool. After detecting this ready status the external de-
velopment tool begins the transmission to the development port with a start bit (logic
high) on the DSDI pin.
is negated (1) otherwise.
Table 21-12 Status / Data Shifted Out of Development Port Shift Register
/
MPC556
0
0
1
1
Status [0:1]
0
1
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Freeze
status
Bit 0
DEVELOPMENT SUPPORT
1
Go to: www.freescale.com
Rev. 15 October 2000
Procedure
Download
progress
Bit 1
in
2
Data
Data
(Depending on Input Mode)
Bits 2:31 or 2:6 —
1’s
1’s
1’s
Table
Valid Data from CPU
Sequencing Error
CPU Interrupt
Null
21-12. “Valid data
Function
MOTOROLA
21-39