MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 394

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

11.6.3 Reserved Location (Bus) and Possible Actions
MPC555
USER’S MANUAL
If the storage reservation is lost, it is guaranteed that a store-with-reservation request
by the CPU will not modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved lo-
cation on the U-bus has been touched by another master. The L2U drives the reser-
vation status back to the core.
When the reserved location in the SRAM on the L-bus is touched by an alternate mas-
ter, on the following clock, the L2U indicates to the CPU that the reservation has been
touched. On assertion of the cancel-reservation signal, the RCPU clears the internal
reservation bit. If an stwcx cycle has been issued at the same time, the RCPU aborts
the cycle.
Storage reservation is set regardless of the termination status (address or data phase)
of the lwarx access. Storage reservation is cleared regardless of the data phase ter-
mination status of the stwcx access if the address phase is terminated normally.
Storage reservation will be cleared regardless of the data phase termination status of
the write requests by another master to the reserved address if the address phase of
the write access is terminated normally on the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx
instruction, the reservation is not guaranteed.
Once the CPU core reserves a memory location, the L2U module is responsible for
snooping L-bus and U-bus for possible intrusion of the reserved location. Under cer-
tain circumstances, the L2U depends on the USIU or the UIMB to provide status of res-
ervation on external bus and the IMB3 respectively.
Table 11-2
/
MPC556
lists all reservation protocol cases supported by the L2U snooping logic.
Freescale Semiconductor, Inc.
For More Information On This Product,
L-BUS TO U-BUS INTERFACE (L2U)
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
11-8