MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 709

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.3.1.1 Restrictions
21.3.1.2 Byte and Half-Word Working Modes
MPC555
USER’S MANUAL
There are cases when the same watchpoint can be detected more than once during
the execution of a single instruction, e.g. a load/store watchpoint is detected on more
than one transfer when executing a load/store multiple/string or a load/store watch-
point is detected on more than one byte when working in byte mode. In all these cases
only one watchpoint of the same type is reported for a single instruction. Similarly, only
one watchpoint of the same type can be counted in the counters for a single instruc-
tion.
Since watchpoint events are reported upon the retirement of the instruction that
caused the event, and more than one instruction can retire from the machine in one
clock, consequent events may be reported in the same clock. Moreover the same
event, if detected on more than one instruction (e.g., tight loops, range detection), in
some cases will be reported only once. Note that the internal counters count correctly
in these cases.
Do not put a breakpoint on an mtspr ICTRL instruction. When a breakpoint is set on
an mtspr ICTRL Rx instruction and the value of bit 28 (IFM) is one, the result will be
unpredictable. A breakpoint can be taken or not on the instruction and the value of the
IFM bit can be either zero or one. Also, do not put a breakpoint on an mtspr ICTRL Rx
instruction when Rx contains one in bit 28.
The CPU watchpoints and breakpoints support enables the user to detect matches on
bytes and half-words even when accessed using a load/store instruction of larger data
widths, for example when loading a table of bytes using a series of load word instruc-
tions. In order to use this feature, the user needs to program the byte mask for each
of the L-data comparators and to write the needed match value to the correct half-word
of the data comparator when working in half-word mode and to the correct bytes of the
data comparator when working in byte mode.
Since bytes and half-words can be accessed using a larger data width instruction, it is
impossible for the user to predict the exact value of the L-address lines when the re-
quested byte/half-word is accessed, (e.g., if the matched byte is byte two of the word
and it is accessed using a load word instruction), the L-address value will be of the
word (byte zero). Therefore, the CPU masks the two least-significant bits of the L-ad-
dress comparators whenever a word access is performed and the least-significant bit
whenever a half-word access is performed.
Address range is supported only when aligned according to the access size. (See ex-
amples)
• Both “go to x” and “continue” working modes are supported for the instruction
/
breakpoints.
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
21-13