MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 158

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

3.12 Instruction Timing
MPC555
USER’S MANUAL
The MPC555 / MPC556 processor is pipelined. Because the processing of an instruc-
tion is broken into a series of stages, an instruction does not require the entire resourc-
es of the processor.
The instruction pipeline in the MPC555 / MPC556 has four stages:
1. The dispatch stage is implemented using a distributed mechanism. The central
/
MPC556
dispatch unit broadcasts the instruction to all units. In addition, scoreboard in-
formation (regarding data dependencies) is broadcast to each execution unit.
Each execution unit decodes the instruction. If the instruction is not implement-
ed, a program exception is taken. If the instruction is legal and no data depen-
dency is found, the instruction is accepted by the appropriate execution unit,
and the data found in the destination register is copied to the history buffer. If a
data dependency exists, the machine is stalled until the dependency is re-
solved.
(Hexadecimal)
01500–01BFF
Vector Offset
00A00
00B00
00C00
00D00
00E00
01C00
01D00
01E00
00000
00100
00200
00300
00400
00500
00600
00700
00800
00900
01000
01100
01200
01300
01400
01F00
Table 3-21 Exception Vector Offset Table
Freescale Semiconductor, Inc.
For More Information On This Product,
Implementation-dependent non-maskable external breakpoint
Implementation-dependent maskable external breakpoint
CENTRAL PROCESSING UNIT
Implementation-dependent instruction protection error
Go to: www.freescale.com
implementation-dependent instruction breakpoint
Implementation-dependent data protection error
Implementation-dependent software emulation
Rev. 15 October 2000
Implementation-dependent data breakpoint
System reset, NMI interrupt
Floating-point unavailable
Floating-point assist
External interrupt
Exception Type
Machine check
Decrementer
System call
Alignment
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Program
Trace
MOTOROLA
3-36