MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 220

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.5 Hardware Bus Monitor
6.6 MPC555 / MPC556 Decrementer
MPC555
USER’S MANUAL
The bus monitor ensures that each bus cycle is terminated within a reasonable period
of time. The USIU provides a bus monitor option to monitor internal to external bus ac-
cesses on the external bus. The monitor counts from transfer start to transfer acknowl-
edge and from transfer acknowledge to transfer acknowledge within bursts. If the
monitor times out, transfer error acknowledge (TEA) is asserted internally.
The bus monitor timing bit in the system protection control register (SYPCR) defines
the bus monitor time-out period. The programmability of the time-out allows for varia-
tion in system peripheral response time. The timing mechanism is clocked by the sys-
tem clock divided by eight. The maximum value is 2040 system clock cycles.
The bus monitor enable (BME) bit in the SYPCR enables or disables the bus monitor.
The bus monitor is always enabled, however, when freeze is asserted or when a de-
bug mode request is pending, regardless of the state of this bit.
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC555 /
MPC556 architecture to provide a decrementer interrupt. This binary counter is
clocked by the same frequency as the time base (also defined by the MPC555 /
MPC556 architecture). The operation of the time base and decrementer are therefore
coherent. In the MPC555 / MPC556, the DEC is clocked by the TMBCLK clock. The
decrementer period is computed as follows:
/
MPC556
15 (Lowest)
0 (Highest)
Priority
16-31
10
11
12
13
14
Freescale Semiconductor, Inc.
1
2
3
4
5
6
7
8
9
SYSTEM CONFIGURATION AND PROTECTION
Table 6-3 Priority of Interrupt Sources
For More Information On This Product,
Go to: www.freescale.com
Interrupt Source
Rev. 15 October 2000
Reserved
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt Code
00000000
00000100
00001000
00001100
00010000
00010100
00011000
00011100
00100000
00100100
00101000
00101100
00110000
00110100
00111000
00111100
—
MOTOROLA
6-12