MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 138

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

CR — Condition Register
MSB
3.7.4.1 Condition Register CR0 Field Definition
3.7.4.2 Condition Register CR1 Field Definition
MPC555
USER’S MANUAL
0
CR0 Bit
The CR fields can be set in the following ways:
Instructions are provided to test individual CR bits.
In most integer instructions, when the CR is set to reflect the result of the operation
(that is, when Rc = 1), and for addic., andi., and andis., the first three bits of CR0 are
set by an algebraic comparison of the result to zero; the fourth bit of CR0 is copied from
XER[SO]. For integer instructions, CR[0:3] are set to reflect the result as a signed
quantity. The result as an unsigned quantity or a bit string can be deduced from the
EQ bit.
The CR0 bits are interpreted as shown in
bit value placed into the destination register) is undefined, the value placed in the first
three bits of CR0 is undefined.
In all floating-point instructions when the CR is set to reflect the result of the operation
(that is, when Rc = 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3]
to indicate the floating-point exception status. For more information about the FPSCR,
see
for the CR1 field are shown in
0
1
2
3
CR0
1
• Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from
• Specified fields of the CR can be moved from one CRx field to another with the
• A specified field of the CR can be set by a move instruction (mcrxr) to the CR
• Condition register logical instructions can be used to perform logical operations
• CR0 can be the implicit result of an integer operation.
• A specified CR field can be the explicit result of an integer compare instruction.
2
3.7.3 Floating-Point Status and Control Register
/
a GPR.
mcrf instruction.
from the XER.
on specified bits in the condition register.
Negative (LT) — This bit is set when the result is negative.
Positive (GT) — This bit is set when the result is positive (and not zero).
Zero (EQ) — This bit is set when the result is zero.
Summary overflow (SO) — This is a copy of the final state of XER[SO] at the completion of the instruction.
MPC556
3
4
5
CR1
6
Table 3-7 Bit Descriptions for CR0 Field of CR
7
Freescale Semiconductor, Inc.
8
For More Information On This Product,
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CR2
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Table
Rev. 15 October 2000
RESET: UNCHANGED
CR3
3-8.
Description
Table
CR4
3-7. If any portion of the result (the 32-
(FPSCR). The bit descriptions
CR5
CR6
MOTOROLA
CR7
3-16
LSB
31