MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 734

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

21.5.6.5 Development Port Serial Communications — Trap Enable Mode
21.5.6.6 Serial Data into Development Port — Trap Enable Mode
MPC555
USER’S MANUAL
Start
Table 21-11 Debug Port Command Shifted Into Development Port Shift Register
Start
1
When in not in debug mode the development port starts communications by setting
DSDO (the MSB of the 35-bit development port shift register) low to indicate that all
activity related to the previous transmission are complete and that a new transmission
may begin. The start of a serial transmission from an external development tool to the
development port is signaled by a start bit. A mode bit in the transmission defines the
transmission as either a trap enable mode transmission or a debug mode transmis-
sion. If the mode bit is set the transmission will only be 10 bits long and only seven
data bits will be shifted into the shift register. These seven bits will be latched into the
TECR. A control bit determines whether the data is latched into the trap enable and
VSYNC bits of the TECR or into the breakpoints bits of the TECR.
The development port shift register is 35 bits wide but trap enable mode transmissions
only use the start/ready bit, a mode/status bit, a control/status bit, and the seven least
significant data bits. The encoding of data shifted into the development port shift reg-
ister (through the DSDI pin) is shown in
1
The watchpoint trap enables and VSYNC functions are described in section
Watchpoints and Breakpoints Support
Table 21-10 Trap Enable Data Shifted into Development Port Shift Register
/
Mode
Mode
MPC556
1
1
Con-
Con-
trol
trol
1
0
1st
Freescale Semiconductor, Inc.
Extended
x
0
1
1
x
x
x
0
1
Opcode
- - - - - - Instruction- - - - - -
For More Information On This Product,
2nd
0
1
0
1
x
x
x
x
x
Watchpoint Trap Enables
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Major Opcode
00100... 11110 Reserved
Rev. 15 October 2000
0 = disabled; 1 = enabled
3rd
00000
00001
00010
00011
00011
00011
11111
11111
11111
11111
Table 21-10
4th
and section
NOP
Hard Reset request
Soft Reset request
Reserved
End Download procedure
Start Download procedure
Negate Maskable breakpoint.
Assert Maskable breakpoint.
Negate Non Maskable breakpoint.
Assert Non Maskable breakpoint.
1st
- - Data- -
and
21.2 Program Flow
2nd
Table 21-11
Function
VSYNC
Transfer Data to
Trap Enable
Control Register
below:
Function
MOTOROLA
Tracking.
21-38
21.3