MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 264

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

8.3.1 Frequency Multiplication
8.3.2 Skew Elimination
8.3.3 Pre-Divider
8.3.4 PLL Block Diagram
MPC555
USER’S MANUAL
The PLL can multiply the input frequency by any integer between one and 4096. The
multiplication factor depends on the value of the MF[0:11] bits in the PLPRCR register.
While any integer value from one to 4096 can be programmed, the resulting VCO out-
put frequency must be at least 15 MHz. The multiplication factor is set to a predeter-
mined value during power-on reset as defined in
The PLL is capable of eliminating the skew between the external clock entering the
chip (EXTCLK) and both the internal clock phases and the CLKOUT pin, making it use-
ful for tight synchronous timings. Skew elimination is active only when the PLL is en-
abled and programmed with a multiplication factor of one or two (MF = 0 or 1). The
timing reference to the system PLL is the external clock input.
A pre-divider before the phase comparator enables additional system clock resolution
when the crystal oscillator frequency is 20 MHz. The division factor is determined by
the DIVF[0:4] bits in the PLPRCR.
As shown in
tor. The phase comparator controls the direction (up or down) that the charge pump
drives the voltage across the external filter capacitor (XFC). The direction depends on
whether the feedback signal phase lags or leads the reference signal. The output of
the charge pump drives the VCO. The output frequency of the VCO is divided down
and fed back to the phase comparator for comparison with the reference signal,
OSCCLK. The MF values, zero to 4095, are mapped to multiplication factors of one to
4096. Note that when the PLL is operating in 1:1 mode (refer to
plication factor is one (MF = 0). The PLL output frequency is twice the maximum sys-
tem frequency. This double frequency is needed to generate GCLK1 and GCLK2
clocks. On power-up, with a four MHz or 20 MHz crystal and the default MF settings,
System Frequency (FREQ
The equation for system frequency (FREQ
• Skew elimination
• Frequency division
/
MPC556
System Frequency (FREQ
When operating with the backup clock, the system clock (and CLK-
OUT) is one-half of the ring oscillator frequency. (i.e., the system
clock is a nominal seven MHz). The time base and PIT clocks will be
twice the system clock frequency.
Figure
Freescale Semiconductor, Inc.
8-3, the reference signal, OSCCLK, goes to the phase compara-
For More Information On This Product,
CLOCKS AND POWER CONTROL
SYS
Go to: www.freescale.com
) will be 40 MHz and the system clock will be 20 MHz.
Rev. 15 October 2000
SYS
) =
NOTE
OSCCLK
DIVF + 1
SYS
) is shown below:
Table
x (MF + 1) x 2 / 2
8-1.
Table
8-1), the multi-
MOTOROLA
8-4