MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 89

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins
2.4.6.1 PRDS Signal
2.4.6.2 Encoded 3-V / 5-V Select
2.4.6.3 Examples
MPC555
USER’S MANUAL
Two signals are needed to enable or disable the pull-up/pull-down devices in the 3-V
/ 5-V multiplexed pads:
The PRDS signal is derived from the PRDS bit in the PDMCR. A single signal controls
all affected pads (all pads related to SGPIO and all pads related to the UIMB modules).
The bit is reset by default (pull-ups enabled) and must be explicitly set by software af-
ter reset. The bit is reset immediately following power-on reset and by hard reset after
data coherency. This bit is not affected by soft reset.
This signal selects between the 3-V functionality and the 5-V functionality of the pin.
5-V operation is selected until the function of the pin is determined (based on the reset
configuration word) and PORESET is negated. At this point the 3-V / 5-V select signal
assumes the intended state (high for 5 V and low for 3 V).
Upon hard reset assertion, if the 3-V / 5-V select line is in 3-V select mode, it remains
in this mode until any external bus access completes. After this the 3-V / 5-V select
signal switches to 5-V mode to enable the pull-ups. This ensures that there is no con-
tention on the bus due to the pull-up being enabled. This signal is not affected by soft
reset.
Each pad group has a 3-V / 5-V select signal. Internal to the pad, logic combines these
signals to control the pull-up.
The combination of this 3-V / 5-V select signal and the resistor disable signal enables
or disables the pull-up.The logic to enable the pull-up is:
pull_enable = PRDS & 3-V / 5-V select
For example, if a pin is configured as a GPIO pin (5 V), the 3-V / 5-V select is high
throughout reset. This causes the pull-up to be enabled. At the end of reset, the 3-V /
5-V select line remains high. The PRDS is high by default until cleared by software.
This causes the pull-up to be enabled until software clears the PRDS bit in the PDM-
CR.
If a pin is configured as a bus pin (3 V), the 3 V / 5 V remains high throughout reset.
This causes the pull-up to be enabled. At the end of reset, the 3-V / 5-V select line goes
low. This causes the pull-up to be disabled, preventing any power loss if the MCU
starts fetching from external memory immediately out of reset.
• The PRDS signal
• An encoded 3-V / 5-V select
/
MPC556
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
MOTOROLA
2-31