MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 472

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.6.1 Port QS Data Register (PORTQS)
MPC555
USER’S MANUAL
DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx
pins are always inputs, regardless of whether they are functioning as SCI pins or as
PORTQS pins.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins de-
fined as outputs. PORTQS reads return data present on the pins. To avoid driving un-
defined data, write the first data to PORTQS before configuring DDRQS.
PORTQS determines the actual input or output value of a QSMCM port pin if the pin
is defined as general-purpose input or output. All QSMCM pins except the ECK pin can
be used as general-purpose input and/or output. When the SCIx transmitter is dis-
abled, TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a dis-
crete input. Writes to this register affect the pins defined as outputs; reads of this
register return the actual value of the pins.
/
MPC556
QSMCM Pin
PCS[0]/SS
NOTES:
PCS[1:3]
MISO
MOSI
SCK
1. SCK/QGPIO6 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which
case it becomes the QSPI serial clock SCK.
1
Table 14-8 Effect of DDRQS on QSPI Pin Function
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
DDRQS Bit
DDQS[4:6]
Go to: www.freescale.com
DDQS0
DDQS1
DDQS2
DDQS3
Rev. 15 October 2000
Bit State
—
—
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Serial data output from QSPI
Serial data output from QSPI
Assertion causes mode fault
Disables chip-select output
Disables slave select input
Serial data input to QSPI
Serial data input to QSPI
Clock output from QSPI
QSPI slave select input
Disables data output
Disables data output
Clock input to QSPI
Disables data input
Disables data input
Chip-select output
Chip-select output
Pin Function
Inactive
Inactive
MOTOROLA
14-10