MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 744

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC555LFMZP40
Manufacturer:
MOTOLOLA
Quantity:
853
Part Number:
MPC555LFMZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
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MPC555
USER’S MANUAL
12:13
14:15
16:17
18:19
29:31
9:11
Bits
0:2
3:5
6:8
20
21
22
23
24
25
26
27
28
/
MPC556
Mnemonic
ISCT_SER
DIWP0EN
DIWP1EN
DIWP2EN
DIWP3EN
SIWP0EN
SIWP1EN
SIWP2EN
SIWP3EN
IWP0
IWP2
IWP3
CTC
CTD
CTA
CTB
IIFM
W1
Compare type of comparator A
Compare type of comparator B
Compare type of comparator C
Compare type of comparator D
I-bus 1st watchpoint programming
I-bus 2nd watchpoint programming
I-bus 3rd watchpoint programming
I-bus 4th watchpoint programming
Software trap enable selection of
the 1st I-bus watchpoint
Software trap enable selection of
the 2nd I-bus watchpoint
Software trap enable selection of
the 3rd I-bus watchpoint
Software trap enable selection of
the 4th I-bus watchpoint
Development port trap enable se-
lection of the 1st I-bus watchpoint
(read only bit)
Development port trap enable se-
lection of the 2nd I-bus watchpoint
(read only bit)
Development port trap enable se-
lection of the 3rd I-bus watchpoint
(read only bit)
Development port trap enable se-
lection of the 4th I-bus watchpoint
(read only bit)
Ignore first match, only for I-bus
breakpoints
Instruction fetch show cycle and
RCPU serialize control
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 21-21 ICTRL Bit Descriptions
Description
DEVELOPMENT SUPPORT
Go to: www.freescale.com
Rev. 15 October 2000
0xx = not active (reset value)
100 = equal
101 = less than
110 = greater than
111 = not equal
0x = not active (reset value)
10 = match from comparator A
11 = match from comparators (A&B)
0x = not active (reset value)
10 = match from comparator B
11 = match from comparators (A | B)
0x = not active (reset value)
10 = match from comparator C
11 = match from comparators (C&D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
0 = trap disabled (reset value)
1 = trap enabled
0 = trap disabled (reset value)
1 = trap enabled
0 = Do not ignore first match, used for “go to x” (re-
1 = Ignore first match (used for “continue”)
These bits control serialization and instruction
fetch show cycles. See
initions.
NOTE: Changing the instruction show cycle pro-
gramming starts to take effect only from the sec-
ond instruction after the actual mtspr to ICTRL.
set value)
Function
Table 21-5
for the bit def-
MOTOROLA
21-48

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