MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 192

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

4.4.7 Error Detection
4.5 Exception Table Relocation
MPC555
USER’S MANUAL
The BE bit defined in
mines whether the BBC operates burst cycles or not. Burst requests are enabled only
when the BE bit is set.
If the IMPU detects access violation, the following actions must be taken:
If the required address contains show cycle or program trace attributes, than the BBC
delivers the access onto the U-bus even if the request is cancelled (due to the excep-
tion it caused).
The way the IMPU notifies the RCPU core for an interrupt is by feeding error informa-
tion into four bits (1, 3, 4 and 10) in the SRR1 register in the core. Only one bit is set
at a time. The exception vector (address) that the core issues for this event is 0xnnn0-
1300. The encoding of the status bits is as follows:
The BBC has the ability to relocate the exception table. Exception table relocation is a
feature to save memory space in the exception table. See
Table
ceptions to be separated by eight bytes instead of 256 bytes (see
location feature maps the exception table into the internal memory space of the
MPC555 / MPC556 and requries MSR[IP] = 1. This feature is important in multi-
MPC555 / MPC556 systems, where more than one MCU can have internal exception
tables with the same exception addresses issued by the RCPU.
The relocation feature also saves the wasted space between exception table entries
when each exception entry contains only a branch instruction to the exception routine,
which is located elsewhere.
If exception relocation is enabled (ETRE bit is set in the BBCMCR), all exception rou-
tines (except the reset exception routine) can be controlled to either remain in the low-
er addresses of the memory (base address + exception offset) BBCMCR[OERC] = 0
or to be relocated to memory (base address + 32 Kbytes) by setting BBCMCR[OERC]
= 1. The reset exception routine location is fixed in memory (base address + the reset
exception offset) and can not be relocated.
See
1. Cancel the request that was forwarded to the burst buffer controller
2. Inform the RCPU core that the requested address generated an exception
• SRR1 = 0
• SRR3 = Guarded storage.
• SRR4 = Protected storage.
• SRR10 = 0
4.6.4 BBC Module Configuration Register (BBCMCR)
/
MPC556
for normal operation of the exception vector table. This is done by mapping ex-
The negated state of the BE bit is useful mainly when the RCPU core
runs in serialized mode. (Refer to
Register
Freescale Semiconductor, Inc.
for the ICTRL register.)
4.6.4 BBC Module Configuration Register (BBCMCR)
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
BURST BUFFER
NOTE
21.7.6 I-Bus Support Control
3.11.5 Exception Vector
for programming details.
Table
4-1). The re-
MOTOROLA
deter-
4-16