MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 951

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

A(0
ACKERR 16-31
Acknowledge error (ACKERR) 16-31
Address
address type (AT0-AT3), 9-37
ALE 21-54
ALEE 21-56
alignment exception, 3-46
ALU–BFU 3-5
AN 13-3, 13-5
Analog
arbitration, 9-30
AT(0
atomic update primitives, 3-42
atomic, 9-31
BAR 3-52
Base ID mask bits 16-30
Baud
BB, 9-7
BDIP, 9-5
BE bit 3-21
Beginning of queue 2 (BQ2) 13-39
BG, 9-7
BI, 9-6
Binary
Bit stuff error (STUFFERR) 16-31
BITERR 16-31
BITS 14-17
Bits per transfer
BITSE 14-23, 14-38
31), 9-4
-mark wakeup 14-58
space 13-7
front-end multiplexer 13-14
input
section contents 13-1
submodule block diagram 13-12
supply pins 13-5
3), 9-4
clock 14-51
divider 13-25
-weighted capacitors 13-14
enable (BITSE) 14-23
field (BITS) 14-17
MPC555 / MPC556
USER’S MANUAL
multiplexed 13-5
port A 13-3
port B 13-4
–A–
–B–
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
INDEX
INDEX
Bit-time 14-50
BKPT (TPU asserted) 17-14
BLC 17-13
BOFFINT 16-31
Boundary conditions 13-17
Boundary scan
BPU 3-5
BQ2 13-17, 13-39
BR, 9-7
Branch
Branch latch control (BLC) 17-13
Branch processing unit 3-5
Break frame 14-51
Breakpoint
Breakpoint counter A value and control register 21-52
Breakpoint counter B value and control register 21-53
BRKNOMSK 21-51
BSC 22-1
BSR 22-1
burst indicator (BURST), 9-36
burst inhibit (BI), 9-39
burst read cycle (illustration), 9-18
burst transfer, 9-15
burst write cycle (illustration), 9-23
BURST, 9-4
Bus
bus busy (BB), 9-32
bus exception control cycles, 9-43
bus grant (BG), 9-32
bus interface
cells 22-1
descriptor language 22-7
register 22-1
prediction 3-5
processing unit 3-5
trace enable 3-21
asserted flag (BKPT) 17-14
flag (PCBK) 17-14
monitor 6-12
off interrupt
bus control signals, 9-2
bus operation
(BOFFINT) 16-31
address transfer phase related signals, 9-35
arbitration phase, 9-30
basic transfer protocol, 9-8
burst mechanism, 9-16
burst transfer, 9-15
bus exception control cycles, 9-43
single beat transfer
single beat read flow, 9-8
MOTOROLA
Index-1