MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 432

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

MPC555
USER’S MANUAL
The QADC64 automatically performs the conversions in the queue until an end-of-
queue condition is encountered. The queue remains idle until the software again sets
the single-scan enable bit. While the time to internally generate and act on a trigger
event is very short, software can momentarily read the status conditions, indicating
that the queue is paused. The trigger overrun flag is never set while in the software
initiated single-scan mode.
The software initiated single-scan mode is useful in the following applications:
External Trigger Single-Scan Mode. The external trigger single-scan mode is a vari-
ation of the external trigger continuous-scan mode, and is also available with both
queue 1 and queue 2. The software programs the polarity of the external trigger edge
that is to be detected, either a rising or a falling edge. The software must enable the
scan to occur by setting the single-scan enable bit for the queue.
The first external trigger edge causes the queue to be executed one time. Each CCW
is read and the indicated conversions are performed until an end-of-queue condition
is encountered. After the queue is completed, the QADC64 clears the single-scan en-
able bit. Software may set the single-scan enable bit again to allow another scan of the
queue to be initiated by the next external trigger edge.
The external trigger single-scan mode is useful when the input trigger rate can exceed
the queue execution rate. Analog samples can be taken in sync with an external event,
even though the software is not interested in data taken from every edge. The software
can start the external trigger single-scan mode and get one set of data, and at a later
time, start the queue again for the next set of samples.
When a pause bit is encountered during external trigger single-scan mode, another
trigger event is required for queue execution to continue. Software involvement is not
needed to enable queue execution to continue from the paused state.
The external trigger single-scan mode is also useful when the software needs to
change the polarity of the external trigger so that both the rising and falling edges
cause queue execution.
External Gated Single-Scan Mode. The QADC64 provides external gating for queue
1 only. When external gated single-scan mode is selected, a transition on the associ-
ated external trigger pin initiates queue execution. The polarity of the external gated
signal is fixed so only a high level opens the gate and a low level closes the gate. Once
the gate is open, each CCW is read and the indicated conversions are performed until
the gate is closed. Software must enable the scan to occur by setting the single-scan
enable bit for queue 1. If a pause in a CCW is encountered, the pause flag will not
set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indi-
cated conversions are performed until an end-of-queue condition is encountered.
When queue 1 completes, the QADC64 sets the completion flag (CF1) and clears the
• Allows software complete control of the queue execution
• Allows the software to easily alternate between several queue sequences
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
MOTOROLA
13-20