MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 694

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

20.3 Programming Model
20.3.1 SRAM Module Configuration Register (SRAMMCR)
MPC555
USER’S MANUAL
The SRAM modules consist of two separately addressable sections the array itself,
and a set of registers used for configuration and testing of the SRAM array. The reg-
isters are located in the SRAM control register block, shown in
Figure 1-3
The control block for each of the two SRAM modules contains one control register for
configuring the array and one control register for use in testing.
Each SRAM module configuration register contains bits for setting access rights to the
array.
/
MPC556
Table 20-1
for the entire MPC555 / MPC556 memory map.
0x38 0000
0x38 0004
0x38 0008
0x38 000C
0x3F 8000
0x3F 8FFF
0x3F 9000
0x3F 97FF
0x3F 9800
0x3F 9FFF
0x3F A000
0x3F AFFF
0x3F B000
0x3F BFFF
0x3F C000
0x3F CFFF
0x3F D000
0x3F DFFF
0x3F E000
0x3F EFFF
0x3F F000
0x3F FFFF
provides definitions for the bits.
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
For More Information On This Product,
MSB
Figure 20-2 SRAM Memory Map
0
Go to: www.freescale.com
SRAMMCR_A
SRAMTST_A
SRAMMCR_B
SRAMTST_B
Rev. 15 October 2000
Sub Block 0
Sub Block 1
Sub Block 1
Sub Block 2
Sub Block 3
Sub Block 0
Sub Block 1
Sub Block 2
Sub Block 3
LSB
31
SRAM Control Registers
6 Kbytes Unused
10 Kbytes SRAM
16 Kbytes SRAM
Figure
20-2. See also
MOTOROLA
20-2