MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 480

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.7.1.2 QSPI Control Register 1
SPCR1 — QSPI Control Register 1
14.7.1.3 QSPI Control Register 2
MPC555
USER’S MANUAL
RESET:
Bit(s)
8:15
MSB
SPE
1:7
0
0
0
SPCR1 enables the QSPI and specifies transfer delays. The CPU has read/write ac-
cess to SPCR1, but the QSPI has read access only to all bits except SPE. SPCR1
must be written last during initialization because it contains SPE. The QSPI automati-
cally clears this bit after it completes all serial transfers or when a mode fault occurs.
Writing a new value to SPCR1 while the QSPI is enabled disrupts operation.
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU has read/write access to SPCR2, but the QSPI has read access
only. Writes to this register are buffered. New SPCR2 values become effective only
after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes ex-
ecution to restart at the designated location. Reads of SPCR2 return the current value
of the register, not the buffer.
/
DSCKL
1
0
MPC556
Name
SPE
DTL
2
0
QSPI enable. Refer to
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
Delay before SCK. When the DSCK bit is set in a command RAM byte, this field determines the
length of the delay from PCS valid to SCK transition. The following equation determines the ac-
tual delay before SCK:
where DSCKL equals is in the range of 1 to 127.
Refer to
Length of delay after transfer. When the DT bit is set in a command RAM byte, this field deter-
mines the length of the delay after a serial transfer. The following equation is used to calculate
the delay:
where DTL is in the range of 1 to 255.
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ F
IMB clock).
Refer to
3
0
Freescale Semiconductor, Inc.
DSCKL
14.7.5.3 Delay Before Transfer
14.7.5.4 Delay After Transfer
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-15 SPCR1 Bit Descriptions
For More Information On This Product,
4
0
5
1
Go to: www.freescale.com
14.7.4.1 Enabling, Disabling, and Halting the
Rev. 15 October 2000
6
0
7
0
Delay after Transfer
PCS to SCK Delay
for more information.
8
0
Description
for more information.
9
0
10
0
=
=
32 D
----------------------- -
DSCKL
------------------- -
f SYS
f SYS
11
0
× TL
DTL
SYS
12
0
SPI.
(204.8 µs with a 40-MHz
13
1
0x30 501A
MOTOROLA
14
0
14-18
LSB
15
0